Radio Frequency (RF) switches that need to withstand large voltages in the off state use stacked Field-Effect Transistor (FET) configurations. Proper operation requires that each FET has direct current bias on its terminals. A typical RF switch may use a stack of n-type FETs (NFETs) and a bias network to control the state of the transistors, e.g., on or off. Various bias resistor configurations exist. A typical bias network is a parallel or series set of resistors for the gates, bodies, and sources/drains of each transistor.
FIGS. 1A, 1B, and 1C show variations of a conventional approach, in which resistor ladders are used for the gate bias network (RG1, RG2, . . . ), the drain and source bias network (RSD1, RSD2, . . . ), and the bulk bias network (RB1, RB2, . . . ). When the switch is off, the gates are biased at ground level or at a negative potential. To turn the device on, the gate-source voltages of the stacked FETs need to go above the positive threshold voltage (Vth). The bias networks may use resistors configured in series, in parallel, in a tree topology, some other topology, or any combination of the above. For example, FIG. 1A shows a shunt branch with series bias architecture, FIG. 1B shows a branch with parallel bias architecture, and FIG. 1C shows a branch with series bias architecture. Other architectures are contemplated.
Table 1, below, lists some typical bias values (in Volts). In the on state, the source, drain, and body bias voltages are set to 0 Volts and the gate is biased to 2.5 Volts. In the off state, the source and drain are biased to 0 Volts but the body and gate are both set to −2.5 Volts, e.g., strongly off. (The body is sometimes referred to as “the bulk.”)
TABLE 1StateVsourceVdrainVbodyVgateon0002.5off00−2.5−2.5
FIG. 1D shows the serial resistance configuration of FIG. 1A, additionally showing the parasitic capacitances at each gate (CG1, CG2, . . . ) and at each source or drain (CSD1, CSD2, . . . ).
Several different parameters should be considered when designing a bias network:
Responsiveness.
The speed of turn-on is limited by the Resistor-Capacitor (RC) time constant set by the gate (front) and drain/source (back) resistors and their corresponding capacitances (CG# and CSD#). For example, referring to FIG. 1D, the first FET in the stack, F1, sees mainly its bias resistors RG1 and RSD1 and parasitic capacitances CG1 and CSD1. The later FETs in the stack F2, F3, and F4 see a distributed RC network with complex Elmore delay times. Therefore, the turning on of the FETs in the switch stack is progressive one-after-the-other and can take a long time in case of large bias resistors and/or large capacitances. In general, it is desirable to reduce the loading resulting from the bias resistor networks, which requires a minimization of the number of resistor branches going to external bias lines (ground, positive, or negative). The specifications of the new Fourth Generation (4G) and Fifth Generation (5G) cellular applications, the Wireless Fidelity (WiFi) specification, and many other applications limit the maximum turn-on and turn-off times. Thus, it is desired to keep the resistance of the bias resistors low so that the switch turn-on time is minimized.
Power Handling.
The resistor network must carry the direct current (DC). In the off state, as the RF voltage differential between the drain and source (VDS) increases, the drain-body and source-body junctions begin to generate current. If the bias network uses very high value resistors, then a DC voltage drop occurs across the bias network, and thus the applied DC voltage is reduced before it reaches the transistor. This causes the power handling to drop. Note that current can flow in the network attached to the body as well as to the source and drain. Thus, it is desired to keep the resistance of the bias resistors low to improve power handling.
Quality Factor.
The Quality Factor (Q) of the switch in off state is set by its bias resistor values. A voltage across a resistor causes power dissipation in the resistor. If the RF voltage induces this power dissipation, then the quality factor is reduced. Therefore, very high value resistors must be used in the bias network to ensure a high quality factor. Typical applications with large and very large bias resistor values are high-Q switched capacitor arrays, for example, Programmable Capacitance Arrays (PACs) or Capacitive Digital-to-Analog Converters (C-DACs). Thus, it is desired to keep the resistance of the bias resistors high to maintain a high Q for the switch.
Thus, there is an intrinsic design trade off to be made: bias resistor values should be kept low to improve responsiveness and power handling but should be kept high to improve quality factor in the off state. What is needed, therefore, is a switch design that provides fast response times and acceptable power handling while providing a high quality factor in the off state.